The NPIC6C4894 is a 12-stage serial shift register. It has a storage latch associated witheach stage for strobing data from the serial input (D) to the parallel open-drain outputs(QP0 to QP11). Data is shifted on positive-going clock (CP) transitions. The data in eachshift register stage is transferred to the storage register when the latch enable (LE) input isHIGH. Data in the storage register drives the gate of the output extended-drain NMOStransistor whenever the output enable input (OE) is HIGH. A LOW on OE causes theoutputs to assume a high-impedance OFF-state. Operation of the OE input does not affectthe state of the registers. Two serial outputs (QS1 and QS2) are available for cascading anumber of NIC6C4894 devices. Serial data is available at QS1 on positive-going clockedges to allow high-speed operation in cascaded systems with a fast clock rise time. Thesame serial data is available at QS2 on the next negative going clock edge. It is used forcascading NPIC6C4894 devices when the clock has a slow rise time. The open-drainoutputs are 33 V/100 mA continuous current extended-drain NMOS transistors designedfor use in systems that require moderate load power such as LEDs. Integrated voltageclamps in the outputs, provide protection against inductive transients. This protectionmakes the device suitable for power driver applications such as relays, solenoids andother low-current or medium-voltage loads.

• Specified from ?40 °C to +125 °C
• Low RDSon
• 12 Power EDNMOS transistor outputs of 100 mA continuous current
• 250 mA current limit capability
• Output clamping voltage 33 V
• 30 mJ avalanche energy capability
• Low power consumption
• Latch-up performance exceeds 100 mA per JESD 78 Class II level A
• ESD protection:
  • HBM JS-2011 Class 2 exceeds 2500 V
  • CDM JESD22-C101E exceeds 1000 V

• LED sign
• Graphic status panel
• Fault status indicator